1. Field of the Invention
The present invention relates to techniques for communicating signals. More specifically, the present invention relates to using on-chip photonics to distribute and to adjust the skew or phase of clock signals.
2. Related Art
Many high-performance circuits or integrated circuits are clocked by a periodic clock signal to coordinate operations between circuit's elements. For example, a microprocessor may run at 2 GHz based on clock signals that have a clock period of 500 ps. In these circuits, it is often necessary to distribute the clock signal such that it reaches all of the targeted circuit elements at the same time (which is sometimes referred to as equal clocking). A variety of existing circuit geometries have been used to achieve this goal, including: H-trees, grids, and/or spines. Unfortunately, even with these circuit geometries, it is difficult if not impossible to achieve equal clocking because of effects such as clock skew and clock jitter.
As shown in FIG. 1, which provides an illustration of existing clock signals 110, clock skew 118 refers to a variation in the arrival time of edges 114 and 116 in clock signal 110-2. This variation is typically systematic and is usually time invariant. In contrast, variations in the arrival time of edges 114 in the clock signals 110 during successive clock cycles are called clock jitter 112. In general, clock jitter 112 includes deterministic and random (or at least uncorrelated) components. Consequently, each version of a clock signal that is distributed to different portions of a circuit typically includes so-called ‘differential jitter.’
Clock skew 118 typically results from the imperfect matching of different clock paths. As shown in FIG. 2A, which provides a block diagram illustrating a semiconductor die 210, a signal line 214-1 that routes clock signals from a central clock circuit 212 (which typically includes a phase-locked loop) to a first target portion of the semiconductor die 210 (such as a circuit 216-1) may have a slightly different length or width than those of signal line 214-2 that routes the clock signals to a second target portion (such as circuit 216-2). This difference may be the result of a design error or a processing inaccuracy. For example, one of the signal lines 214 may have more sidewall capacitance than the other, which results in both static and dynamic differences in capacitance between the two signal lines 214.
A typical design constraint for clock jitter 112 (FIG. 1) is approximately 5% of the delay associated with the entire clock path (which is sometimes referred to as the ‘insertion’ delay) or 10% of the clock period. (Note that design constraints are even more stringent in circuits that include multiple clock signals, such as multi-phased clock signals.) However, it is often difficult to reduce or eliminate clock skew 118 (FIG. 1) because mismatches between clock paths rarely arise until after a layout is completed and the performance of the design is extracted using simulations. Unfortunately, the extraction process is complicated and has limited accuracy.
Clock jitter 112 (FIG. 1) has a variety of sources, including power-supply noise and crosstalk (for example, between adjacent signal lines). For example, as power-supply voltages rise and fall the delays associated with elements along clock paths will also vary. These variations in the clock-path delay can lead to cycle-to-cycle differences in the arrival times of clock edges (such as clock edges 114 in FIG. 1). Note that a design constraint for clock jitter 112 (FIG. 1) is typically approximately 5% of the clock period. Unfortunately, aside from decreasing the overall insertion delay, further reducing or avoiding clock jitter 112 (FIG. 1) is difficult.
Furthermore, distributing clock signals also consumes power. For example, distributing clock signals in existing high-performance microprocessors may consume up to 20% of the total chip power. As clock frequencies continue to increase, this power consumption is becoming an increasing burden and is creating challenges for circuit designers.
Moreover, many systems benefit from using multi-phase clock signals for circuits such as oversampled receivers. These multi-phase clock signals are either generated at the receivers (at high area and power cost) or are distributed from a central clock source (with the associated clock skew and jitter problems discussed above).
Hence, what is needed is a method and an apparatus that facilitates distribution of clock signals without the problems listed above.